Static Analysis of Parameterized Loop Nests for Energy EÆcient Use of Data Caches

Caches are an important part of architectural and compiler low-power strategies by reducing memory accesses and energy per access. In this paper, we examine eÆcient utilization of data caches for low power in an adaptive memory hierarchy. We focus on the optimization of data reuse through the static analysis of line size adaptivity. We present an approach that enables the quanti cation of data misses w.r.t. cache line size at compile-time. This analysis is implemented in a software package STAMINA. Experimental results demonstrate e ectiveness and accuracy of the analytical results compared to alternative simulation based methods.